While the subject invention provides a new product and process, a related process is set forth in U.S. Pat. No. 4,231,051 issued to the same inventors on Oct. 28, 1980. This is the closest known prior art and while it teaches employing a first and second layer of polysilicon in processing, it does not teach the provision of a redundant ROM cell comprising a FET and drain connected series resistor nor a process for fabricating the same, wherein the resistor is manufactured from the second undoped polysilicon layer and the cell is programmable by irreversibly changing the resistor from a high resistance value to a highly conductive value through the application of a biasing voltage when the associated FET is conductive.